The present invention relates generally to a method for fabricating Dynamic Random Access Memory (DRAM), and more particularly, to method and device for providing double cell density in Synchronous Dynamic Random Access Memory (SDRAM) and in Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).
Dynamic random access memory (DRAM) is an important device, which saves digital data. A synchronous dynamic random access memory (SDRAM) is one kind of DRAM that is synchronized with operation speed and clock signal. Heretofore, in order to further improve the operation speed, a concept of a double data rate (DDR) synchronous dynamic random access memory (SDRAM) has been extensively used. A conventional SDRAM employs only a rising edge of a clock signal, while the DDR SDRAM employs both rising and falling edges of the clock signal.
A conventional trench type device is used in the SDRAM or DDR SDRAM as a capacitor. FIG. 1 shows a cross-sectional diagram of a trench type DRAM according to the prior art. The trench type DRAM was formed on semiconductor substrate 10. Each trench type DRAM contains a p-type well 12, a trench capacitor 14, shallow trench isolation (STI) 16, a buried strap 18, a word line 20 and a contact window 22. Particularly, the word line 20 such as a sandwich structure contains a polysilicon layer 20a, a tungsten silicide layer 20b and a silicon nitride 20c from bottom to top. The difficulties of integration DRAM fabricating process, as shown in FIG. 1, are that either the size of conventional trench type DRAM which needs large area to store more charge is hard to scale down or the fabrication cost of trench type DRAM cannot be decreased.
Generally, data retention time and device reliability are two major issues in DRAM fabrication. Lowering leakage current of DRAM and raising cell density are two primary targets for DRAM fabrication under the circumstance, which varies fewer process steps and applies the existing IC technology.
On the other hand, a vertical MOS has been applied in wireless communication such as that disclosed in U.S. Pat. No. 6,184,090, entitled xe2x80x9cFabrication Method For a Vertical Transistorxe2x80x9d by United Microelectronics Corporation (UMC), but the vertical MOS device is not applied yet in DRAM fabrication. The vertical MOS device is formed on a semiconductor substrate 30. Referring to FIG. 2, each vertical MOS device contains a STI 32 (shallow trench isolation), a first doping layer 34, a second doping layer 36, a third doping layer 38, a gate oxide layer 40, a gate conductive layer 42 and a dielectric layer 44.
Embodiments of the present invention are directed to devices and methods for providing double cell density in SDRAM and in DDR SDRAM.
An aspect of the present invention is directed to a method for providing double cell density in SDRAM and in DDR SDRAM. First, a conventional photolithography technology is used to define a cell area on a semiconductor substrate. An array device active area is defined on the cell area and STIs are formed beside the array device active area in the semiconductor substrate. A trench capacitor is subsequently formed in the array device active area. Next, a polysilicon layer is subsequently deposited, photolithographed and anisotropically etched to form an array device on the trench capacitor.
A gate oxide layer, a gate conductive layer and a gate cap are subsequently formed on the array device polysilicon layer according to following steps. A silicon oxide layer is thermally oxidized, a polysilicon/ tungsten-silicide layer and a gate cap layer are subsequently deposited on the semiconductor substrate and then the horizontal portions of the three layers on STI are removed by the procedure of anisotropic etching. A contact window is formed on the polysilicon layer of the array device active area. The top portion of the array device active area is doped with ion implantation through the contact windows. Finally, the contact window is filled with polysilicon to form a contact plug.
In accordance with another aspect of the present invention, a device is provided with double cell density in SDRAM and in DDR SDRAM. A SDRAM or a DDR SDRAM is set on a cell area of a semiconductor substrate. STIs are formed beside the array device cell area in the semiconductor substrate. Each SDRAM or DDR SDRAM contains a trench capacitor and an array device. Particularly, the array device on the cell area comprises an array device polysilicon layer, a gate oxide layer, a gate conductive layer, a gate cap and a contact plug. The trench capacitor is set in the array device active area of the semiconductor substrate. In other words, the upper edge or level of the trench capacitor substantially coincides with that of the substrate surface. Furthermore, the trench capacitor contains a trench, an oxide-nitride layer, a first polysilicon layer, an oxide layer, a second polysilicon layer and a buried strap. Particularly, the trench is set in the array device active area of the semiconductor substrate. The oxide-nitride layer formed along the shape (bottom and sidewall) of the lower portion (e.g., lower half) of the trench is set on the lower portion of the trench. The lower portion of the trench is then filled with the first polysilicon layer surrounded by the first oxide layer. The oxide layer formed along the upper portion sidewall of the trench is set on the first oxide layer and a part of the first polysilicon layer. After that, the second polysilicon layer surrounded by the second oxide layer is set on top of the first polysilicon layer. More particularly, the upper edge or level of the second polysilicon layer is higher than that of the oxide layer. The buried strap which fills the rest of the trench is then set on the oxide layer and the second polysilicon layer. The upper edge or level of buried strap substantially coincides with that of said semiconductor substrate.
In the vertical MOS device, the trench capacitor of the cell area is covered with the array device polysilicon layer of the array device. The gate oxide layer is set upon the array device polysilicon layer of the array device active area and the gate conductive layer is set upon the gate oxide layer. Finally, the gate conductive layer as a word line comprised of polysilicon/tungsten-silicide is covered with the gate cap, which contains a gate nitride layer. An insulating spacer set on sidewall of the gate oxide layer, the gate conductive layer and the gate cap layer and adjacent to the contact plug. The contact plug comprised of polysilicon is set on the array device polysilicon layer of the array device active area. A doping area which is the bottom of the contact plug connects the array device polysilicon layer of the array device active area and also tunnels the gate oxide layer, the gate conductive layer and the gate cap.
FIG. 1 is a cross-sectional diagram of the trench cell capacitor of DRAM according to the prior art;
FIG. 2 is a cross-sectional diagram of the vertical MOS according to the prior art;
FIG. 3 is a cross-sectional diagram illustrating a process of forming the deep trench and the second oxide layer according to an embodiment of the present invention;
FIG. 4 is a cross-sectional diagram, illustrating a process of forming the trench capacitor according to an embodiment of the present invention;
FIG. 5 is a cross-sectional diagram illustrating a process of forming the STIs according to an embodiment of the present invention;
FIG. 6 is a cross-sectional diagram illustrating a process of forming the polysilicon layer according to an embodiment of the present invention;
FIG. 7 is a cross-sectional diagram illustrating a process of forming an array device polysilicon layer of the array device active area according to an embodiment of the present invention;
FIG. 8 is a cross-sectional diagram illustrating a process of forming the gate oxide layer, the gate conductive layer, the gate tungsten silicide layer and the gate nitride layer on the array device active area according to an embodiment of the present invention;
FIG. 9 is a cross-sectional diagram illustrating a process of forming the doping area through the contact window according to an embodiment of the present invention;
FIG. 10 is a cross-sectional diagram illustrating a process of forming double cell density in SDRAM and in DDR SDRAM according to an embodiment of the present invention.